Intel Unveils 18A-Built Xeon 6+ Data Center CPUs, Clearwater Forest AI Chips And More At Computex
by Zak Killian — Sunday, May 31, 2026, 11:00 PM EDT
Intel brought along a pile of products to Computex, and while the one that got this writer most excited was the early announcement of the Arc G3 series, the company's data center group has some pretty darn big news, too. Today marks the launch of the Intel Xeon 6+ processors, codenamed Clearwater Forest, but they're not the only news, just the biggest.
So we'll start there. Clearwater Forest is Intel's latest server product, featuring up to 288 Darkmont CPU cores in a single socket. Built on its most cutting-edge 18A fabrication process, Xeon 6+ offers what Intel says is "market-leading rack density" and what it claims is the best performance per thread on the market. That claim seems silly when you think that it's made up entirely of E-cores, but therein lies the trick: E-cores don't have Hyper-Threading, so where a Zen 5 processor is using one core to serve two threads, Intel can simply give both threads their own core.
The specs of the Xeon 6+ parts seem almost nonsensical on paper. Up to 288 real cores, not logical cores; there's no abstraction or fakery here. 576 megabytes of last-level cache, served by twelve channels of DDR5 running at up 8 GT/s thanks to MRDIMMs. Up to 96 lanes of PCI Express 5.0 connectivity, and up to 64 lanes of CXL for extremely high-speed links to peripherals. TDPs scale up to 450W, although there are lower-end parts with smaller cooling requirements.
The Clearwater Forest chips use no less than twelve separate compute tiles, fabbed on Intel's own 18A process. Those rest upon three active base tiles, which are flanked by a pair of I/O tiles re-used from the Xeon 6900-series Granite Rapids Xeons. Twelve EMIB tiles are used to connect everything together with Foveros Direct technology, enabling ultra-low-latency communications across the whole chip.
The Darkmont core architecture is of course an E-core architecture, and so it follows that one of the big new features of Clearwater Forest is focused on improving power efficiency. Intel AET, "Application Energy Telemetry", allows datacenter operators to monitor per-core, per-application energy usage at the hardware level. This makes it easier for system admins to identify problem workloads and improve energy efficiency through software optimizations or simply environment modifications.
This slide compare Clearwater Forest to the first-gen E-core only Xeons, Sierra Forest. Besides doubling the CPU core count, these chips radically increase memory bandwidth and last-level cache, which should help tremendously with memory-bound workloads. The new Xeon 6+ chips also feature additional cryptographic acceleration instructions for SHA-512, SM3, and SM4 encryption schemes that Intel says offer as much as a 15× performance jump over last-generation, and as much as 6× speed over AMD's EPYC 9965.
Comparing against its own previous-generation Sierra Forest parts, Intel says that the new parts offer an enormous 126% performance uplift while offering 55% better performance per watt; if you do the math, that means they're also consuming about 46% more power. That's not bad at all considering that the new parts have literally doubled the core count and increased the last-level cache by a factor of five. Of course, the benchmarks here are carefully chosen to represent the best case for a massively multi-core processor like this, but then, why would you buy a chip like this to run anything but embarrassingly parallel workloads?
Intel also unusually doesn't shy away from comparisons against the competition, pitting the top-end Xeon 6990E+ against an AMD EPYC 9965. That's a 192-core Turin chip with relatively low-clocked Zen 5c cores, making it a reasonable comparison point for Clearwater Forest. Intel claims a win in both performance per thread and "average performance per thread per watt", although if we look at both claims, it means the chips consumed roughly the same amount of power, yet AMD's chip was actually very slightly faster. (384 threads = 288 * 1.333..., which is larger than the 30% performance claim.) So the EPYC part is actually more efficient overall, interestingly.
Of course, plenty of workloads won't fully load the chip that way, so a per-thread efficiency advantage is still meaningful. As Intel itself notes in this slide, CPU utilization of around 40% is probably more typical of the kind of workload chips like this will experience. In that case, Intel claims to beat AMD's chip by 30% in overall performance per watt, while the two lines seem to converge as CPU utilization goes up.
Finally, this slide condenses Intel's claims. Ultimately Clearwater Forest is an obviously huge uplift over Sierra Forest, but whether it's actually useful for your workload is going to depend tremendously on whether you need massive multi-core throughput or extreme single-threaded performance. In the former case, it's awesome; in the latter case, you might want to wait for Diamond Rapids.
Intel didn't have much to say about Diamonds Rapids at Computex, but it did confirm rumors that the chips were delayed. Indeed, the next-generation all-P-core Xeons are coming next year, featuring 16-channel memory, PCI Express 6.0, up to 192 cores per socket, and notably, a move to Intel's "18A-P" process, the refined version of the fabrication technology. Intel says 18A-P reduces thermal resistance by a third (improving conductivity by 50%) and offers an 18% efficiency improvement at the same clock rates over the current 18A process; those are huge gains for a process refinement, and should translate directly into making Diamond Rapids more competitive against the Zen 6 "Venice" CPUs that will be available when it launches.
THe other big announcement Intel has for today is the launch of its new Ethernet E835 network adapter. This is a new NIC with a PCI Express 5.0 x8 interface supporting up to 200 Gigabits of Ethernet throughput. Intel says that the chip itself supports configurations ranging from 4x 25-Gigabit up to 1x 200-Gigabit. It's also available in an OCP form factor, and according to Intel, it offers nearly double the power efficiency of NVIDIA's ConnectX-6 adapter.
This slide has the full list of specifications that Intel offered, including clock synchronization, advanced manageability features, support for both Linux and Arm as well as Windows and ESXi, robust virtualization and security support, and more. What Intel didn't give was pricing or availability information, but it did say that its enterprise partners (like Cisco, Dell, HPE, Lenovo, and Supermicro) will be offering the new NIC.
Last but not least, Intel also gave an update on Crescent Island, which is indeed still happening. The next-generation Intel Data Center GPU will be based on the Xe3P GPU architecture, will support datatypes ranging from FP4 to FP64, and will be able to support up to a whopping 480GB of local memory, although Intel's own-branded add-in cards will come with "only" 160GB. Interestingly, Crescent Island uses LPDDR5X instead of GDDR, which is how it enables such massive capacity. The chip has a 350W TDP in PCIe form factor; it's not clear if it will support OCP. It's also not clear when these chips will launch, nor for how much.
Intel's Computex data center showcase proves that the company isn't just fighting for raw performance crowns anymore. Instead, the house that Pentium built is playing a calculated game of architectural specialization. The datacenter is where Intel is facing its harshest competition, and it's clear that the company feels the heat, but it's also clear that it's too early to count Team Blue out just yet. We're keen to see how Intel's next-gen parts perform in the real world, so stay tuned for when we have that data on hand.
