Dmitry Grinberg published a lengthy piece detailing his dissatisfaction with RISC-V, which can be read here: RISC-V: They Should Have Known Better - Dmitry.GR. The article reached the front page of Hacker News and sparked a significant discussion on Lobsters. It represents one of the most substantial criticisms the architecture has faced recently. Although I transitioned my entire development stack from STM32 and ARM to RISC-V about a year ago and even created a video about it Goodbye STM32 ARM – Meet the CH32 RISC-V Chips That Replaced It!, a part of me is incensed because much of his critique appears to stem from a biased viewpoint.
I am not here to defend the ISA committee; RISC-V International denied me membership to their exclusive circle. Regarding the architecture itself, the compressed store offsets are indeed peculiar, and Zicsr really should not be a separate extension that one must explicitly request. I have encountered all of these issues and have written a book, approximately 80% complete, detailing these challenges on the CH32V003, which is one of the "RV32E" type chips he mentions.
Perhaps I should clarify my location, as it significantly influences which aspects of this discussion appear most important from my perspective.
I operate from Trinidad and Tobago, a small island nation off the coast of Venezuela. When I need a development board, I'm not clicking through to next-day delivery. Instead, I'm checking if the seller even ships here, what customs might do to it (if I receive it at all), and the final cost in TT dollars. "Free Shipping" from Digikey, Mouser, or any US or European manufacturer is not applicable to me. I pay anywhere from US $60 to US $200 to ship chips that cost a dollar, which people elsewhere receive with free shipping. In fact, a well-known PCB company that approached me about potential sponsorship turned me down solely based on shipping to my location.
The students I aim to teach are in the same predicament, as are those in Nigeria, Bangladesh, and other places that the industry overlooks when writing blog posts. From this vantage point, the difference between a ten-cent part and a one-dollar part is not a rounding error or a minor detail to be glossed over in favor of discussing encodings. It is the difference between a class of thirty students each having their own chip and a class of thirty students watching a single demo board, if they get one at all. Instruction set elegance is a luxury one can afford to care about once the hardware is already on your desk. Whether the hardware can reach your desk at all takes precedence. That is why the paragraph most readers likely scrolled past is, to me, the most crucial in the article.
Grinberg missed the point that RISC-V creates an opportunity for the other 99% outside of "the world" (which in this context primarily means the US and Europe), and this has nothing to do with the architecture.
He Derives the Requirements and Lands on RV32EC
Before delving into interrupt arithmetic or encoding complaints, he undertakes a careful analysis. He questions the purpose of a low-cost microcontroller core. His conclusion is that it resides within a larger chip, managing registers and configuring hardware blocks in devices like "an MP3 player, an SD card, a USB stick." The primary processing is handled by custom silicon surrounding it. From this, he deduces the core's essential needs: low interrupt latency, a small die area, and good code density, as the code resides in ROM or SRAM, both of which are costly per byte. He suggests no hardware divider, possibly not even a multiplier, given the limited arithmetic operations. He also posits no need for privilege separation, as no untrusted code runs on it.
Then he writes this line himself:
"But," you might say, "you just described RV32IC (or RV32EC)!"
And earlier, plainly:
I am 100% sure that RISC-V will own the cheap-as-dirt single-use microcontroller space eventually.
So, the most credible RISC-V critic of the month sat down, reasoned from first principles what a low-cost microcontroller core should be, arrived at the instruction set implemented by a ten-cent chip, and declared that this segment will be dominated by RISC-V. He establishes the case for the chip and then spends the remainder of the article expressing frustration that such a chip exists.
This is almost satirical.
His contention is about whether this outcome was deserved. That is a valid question and I understand why it troubles him. However, it is not a question that impacts anyone deciding what to learn on, as the chip is available regardless.
Where I Actually Disagree, Strongly.
His central assertion, the first one in the article, is more significant than any of the encoding complaints:
Simply put, the things a high-end CPU needs are diametrically opposed to the things a small cost-saving microcontroller core needs.
The conclusion he draws is that no single ISA can serve both purposes, and that RISC-V proponents are deluding themselves. In theory, the premise is sound. However, the conclusion does not logically follow, and I can demonstrate why using three components currently on my desk.
CH32V003. This is the inexpensive "RV32EC" with sixteen registers, no multiplier, no divider, machine mode only, 2KB of SRAM, 16KB of flash, costing ten cents. It is precisely the core he specified. I have shipped two products utilizing these chips: one is a bin monitor with a ToF sensor, an LED, and an air tag. The other is an agricultural product for a client that automates door opening and closing at specific times. It also serves as an excellent disposable component, as demonstrated in my whistle switch project Clap Switch Is Dead. Here's the RISC-V Powered Whistle Switch!. In my opinion, it is the ideal replacement for the overpriced, outdated Arduino Did Arduino Q Ruin Arduino? - Here's how to Switch to RISC-V with the CH32V003.
CH32H417. This is a dual-core MCU offering an unparalleled performance-to-price ratio, positioned at the higher end of the MCU spectrum. It features a QingKe V5F running at 400 MHz alongside a V3F at 144 MHz, with 896KB of SRAM and 960KB of flash. It includes USB 3.2 Gen1 with an integrated 5 Gbps transceiver, 100M Ethernet MAC and PHY, an isolated SerDes transceiver, a 500 MB/s high-speed interface, SDMMC, a camera interface, a display controller, and a graphics accelerator, among other features. I successfully ran a web browser on this device I Built a Web Browser on a RISC-V Microcontroller (No Linux), performed Quantum entropy-based GAN cat generation Schrödinger's De/Motivational Quantum Cat: GAN Image Generation on CH32 RISC-V Microcontroller, and implemented real-time facial recognition Real Time Facial Recognition on The Edge With CH32H417 RISC-V MCU using less than 150KB of RAM. I have numerous other projects running, but these are a few I've had time to record and publish.
Baochip. This is a VexRISC-V with an MMU, built around an open-source stack from silicon to OS Baochip-1x: A Mostly-Open, 22nm SoC for High Assurance Applications « bunnie's blog. It runs Xous betrusted-io/xous-core: The Xous microkernel, developed by the legendary hardware hacker "bunnie" Huang. It's a Rust microkernel with genuine process isolation and privilege separation, precisely what he claims the low-cost segment doesn't need and therefore doesn't get. In addition to Xous, it also supports operating systems like SEL4 vk2seb/bao1x-seL4: seL4 port to baochip-1x and Linux pkoscik/baochip-linux: An attempt to boot mainline Linux on a stock Dabao board. I developed the bare-metal C SDK for the chip ArmstrongSubero/dabao-sdk: Bare metal C SDK for the Baochip-1x RISC-V SoC. Notably, it was the chip featured in the DEFCON 34 badge this year The New Defcon Badges Pack a Unique Open Source Chip That Doubles as a Security Key | WIRED.
I can also point to the NES emulator I wrote for the $1 ESP32C3 RISC-V based chip NES Emulator on $1 ESP32-C3 RISC-V Microcontroller, or my experiments with Linux on the Orange Pi RV2 OrangePi RV2 5 Minute Unboxing and Setup | RISC-V Ubuntu Linux, which took five minutes to set up and has been running flawlessly since its initial boot.
The point is, I could continue indefinitely about how diverse and accessible the currently available RISC-V parts are, but that would stray too far from the topic at hand.
I've linked all these examples to illustrate that all these components share the same base instruction set, and I gained expertise across them all in under a year and for under US $100 for the entire stack, from disposable silicon to PC-level capabilities, excluding data center compute.
For under US $100, including shipping, I was able to explore an entire vertical stack using a single architecture. Due to the AI race, the OrangePi RV2 has increased in price, but at its release, it cost $30 and included free shipping. For approximately $7, I acquired 50 CH32V003s with a debugger. The CH32H417 board costs $20 on Analog Lamb and uses the same inexpensive (and official) debugger as the CH32V003. The Baochip Dabao board (which I've written a book about, available here: The Dabao Book - Payhip) cost $9.50 on Crowd Supply when I purchased it; two units with shipping from Crowd Supply totaled $35, well under $100. A debugger for an ARM part, such as a Segger J-Link, costs around $600. Alternatively, for that $100, plus another $100 for shipping (totaling about $200), I could obtain an EDU edition J-link, but no chips or boards. Yay.
Returning to RISC-V, across all these components, the base set remains consistent. This implies the same register model, calling convention, and toolchain. While extensions do vary, the fundamental knowledge gained from writing assembly on the ten-cent CH32V003 remained applicable to all other components, whether it was a dual-core MCU, an SBC running Linux, or an advanced custom security chip running a novel operating system. My skills were transferable to the point that in each case, within a few hours, I had toolchains set up, could focus on my applications, and felt comfortable during debugging. All I require to work with them is the ISA manual and a C compiler.
Now, consider the equivalent journey on the other side. Let's set aside x86-64 with its duopoly, patent minefield, and multi-thousand-dollar debug probes, and focus on ARM.
The equivalent to the CH32V003 is the Cortex-M0, which is ARMv6-M, such as the STM32F030. Stepping up, we have the Cortex-M7, which is ARMv7-M. To obtain an MMU in a chip suitable for Linux or SEL4 and Xous, you're looking at an application processor like the ARMv8-A. These are different ARM profiles with significantly different privilege, exception, and system models. Therefore, moving up the stack involves substantially more relearning than simply enabling another RISC-V extension. Trust me, I've used them all.
And at the upper end of that range, the gap is not even about learning curves. There is no Cortex-M microcontroller with an integrated USB 3.0 SuperSpeed PHY. The closest dual-core ARM part is an STM32H747, which is a capable chip but lacks this feature. If you require USB 3.0, you must leave the microcontroller class entirely and move to an i.MX 8 or an RK3xxx, which implies a Cortex-A. You'll need an MMU, Linux, DDR, a PMIC, and a board that isn't laid out on two layers. Alternatively, you can keep the M7 and add an external bridge chip.
The H417 evaluation board costs around twenty dollars. The H747 in TFBGA240 has a twenty-week manufacturer lead time, chip only, and costs about the same, before you add any peripherals. Mouser requires identification before you can order, and Digikey has also been known to deny orders based on location. Hussein Ali, a well-known YouTuber from NorthridgeFix, describes such an experience Starlink Repair - Digi-key refused my order.. Oh, and shipping to my location costs about US $60-100+. I can purchase H417s on the official WCH store on Aliexpress with free shipping and no verification hassle. We haven't even begun discussing the Cortex-A parts with MMUs, their debugging tools, and ecosystem fragmentation.
The Boundary Is Not Technical
Here's the aspect that most directly undermines his framing, and it has nothing to do with encodings. He treats the gap between a small core and a large one as an architectural fact, a consequence of opposing requirements. On ARM chips, this is not an architectural fact; it is a PRODUCT boundary enforced by licensing. Has anyone attempted to add an MMU to a Cortex-M? The physical trade-offs are real, but the difference is that with RISC-V, the ISA owner does not dictate where that boundary must be drawn. If you want virtual memory on ARM, you license a Cortex-A, which is a different core family, a different profile, a different negotiation, and a different royalty. There is no incremental path; there is a wall, with a sales team on the other side.
Compare this to what happened with Baochip. The RISC-V privileged specification defines supervisor mode and Sv32 paging as optional features an implementation may provide. VexRISC-V is an open core, and someone added an MMU to it. "bunnie" built a chip around it and runs a microkernel with true process isolation on it. This allows me, in Trinidad, a country whose name doesn't even appear in ISA discussions, to experiment affordably and teach others in the region.
That is what freedom looks like.
No one asked for permission, no one signed anything, no one pays a royalty per unit shipped, and anyone can learn down to the RTL level of the silicon's construction. So, when Grinberg lists privilege separation among the features the low-cost segment doesn't need and therefore doesn't get, he is describing a characteristic of ARM's product segmentation and attributing it to instruction set design. On RISC-V, it's a checkbox in the privileged spec. You omit it in a ten-cent part because it adds area you don't want to spend, and you enable it when needed, with the underlying instruction set remaining the same.
That is the fundamental difference between the two ecosystems, and it's why "one ISA cannot serve both ends" sounds different depending on your perspective. On one side, the ends are separated by physics and cost; on the other, they are separated by physics, cost, and a contract.
The Thing He Calls Fragmentation
Before concluding, I want to address his stance on fragmentation. He is not incorrect that the extension mechanism fragments the standard. Zcb splitting off from C is inconvenient, and Zicsr not being implied by the base is also annoying. Vendors adding proprietary interrupt hardware further fragments things; I learned this firsthand while porting NuttX to the CH32V307 Porting Apache NuttX RTOS to the WCH CH32V307: A Deep Dive into the PFIC and Everything That Went Wrong.
However, this mechanism is the solution to his opening question. The reason a single instruction set can be used in a ten-cent part with sixteen registers and also in a chip running a protected multi-process operating system is precisely because the small part is not burdened by the requirements of the large part. There is no compromised core in the middle serving both poorly, which is what "diametrically opposed requirements" would typically necessitate. Fragmentation and scalability are two sides of the same coin; you cannot have one without the other, and whether the trade-off was worthwhile is a fair debate with no obvious answer.
What I do believe is that he is right about the crucial aspect, and in a way that favors the very thing he is criticizing. RISC-V will not dominate the low-cost microcontroller market due to its elegant encoding. It will achieve this because the parts cost ten cents, and because the progression upwards utilizes the same instruction set. It is succeeding because an embedded engineer in a third-world country can illuminate a cheap LED and observe the transistors within the silicon Infra-Red, In Situ (IRIS) Inspection of Silicon « bunnie's blog, and obtain 50 chips with a debugger and free development tools for the price of a cup of coffee, with free shipping. It also enables world-class engineers to design MMUs onto chips that gatekeepers would never license.
He writes that this will happen "not due to its ISA design, but despite it," intending it as a mild indictment. From my perspective, it is not. Winning on price and availability is not a lesser form of victory. It determines who gets a seat at the table. An architecture that arrives in my country at ten cents per part, with an open toolchain and no license to negotiate, makes embedded systems accessible to individuals who previously could only watch others' demo boards and consume their products without ever being able to replicate their access. That is the power of freedom, openness, and true democracy.
That is a more compelling reason than elegance. And I wish to inform Mr. Grinberg that the word "privilege" he uses throughout his article extends beyond the ISA, depending on one's location in the world.
Enough said.
Armstrong Subero is an embedded systems engineer and published author with Apress/Springer. He develops the Rovari RISC-V education platform from Trinidad and Tobago.
