3-2 | A14 CMOS NanoFlexTM Pro Platform Technology with 2nd Gen. Nano-sheet and Full Node PPA Benefits for HPC/AI and Mobile SoC Applications
Description
Authors: Shien-Yang Wu, Taiwan Semiconductor Manufacturing Company (TSMC) | Chih-Hao Chang, Taiwan Semiconductor Manufacturing Company (TSMC)
Speakers
Presenting Author
Taiwan Semiconductor Manufacturing Company (TSMC)
Tracks
Parent Sessions
- Mon. Dec. 14 | 1:45 PM - 4:45 PM – 3 | ALT | Platform and DTCO
Abstract
A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 1015% speed enhancement, a 2530% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.
