Can transistors really become smaller than 4 nanometers? KAIST has the answer
Published on June 20, 2026 at 5:30 PM by Christian D.
The semiconductor industry is engaged in a perpetual quest: to etch ever-smaller components to increase computing power and reduce energy consumption.
However, this ambition runs into a fundamental obstacle. Researchers at the prestigious KAIST institute, led by Professor Yong-Hoon Kim, have developed an unprecedented calculation method to precisely define the boundaries of this miniaturization.
Their approach, published in the journal npj Computational Materials, relies on a purely theoretical simulation based on the fundamental laws of physics and capable of predicting the minimum achievable size for transistors.
Why is transistor miniaturization blocked?
The main barrier to reducing transistor size is a phenomenon called quantum tunneling. Specifically, when components become excessively small, electrons begin to "leak" through insulating barriers they should not normally be able to cross.
This chaotic behavior makes controlling electric current extremely difficult, if not impossible, and nullifies the very function of the transistor, which is to act as a reliable switch.
Until now, determining the exact point where this effect becomes problematic was a real headache. It is virtually impossible to directly observe and measure interactions at the atomic scale where metallic electrodes come into contact with the semiconductor channel.
Manufacturers therefore proceeded partly by trial and error, a lengthy and incredibly expensive process, and a change in method had become essential.
What solution do KAIST researchers propose?
Professor Kim's team circumvented the experimental problem by using a computational approach. They relied on ab initio calculations, a method that predicts material behavior based solely on fundamental physical laws, without experimental data.
The core of their innovation lies in a virtual design platform built on a theoretical framework they had already developed, MS-DFT (multi-space density functional theory).
This platform allows them to simulate experiments to measure contact resistance and, above all, to determine the "critical tunneling length". This is the size at which electron leakage begins to disrupt transistor operation.
In short, they have created a true virtual laboratory to test chip configurations before even considering their fabrication.
What are the concrete results of this simulation?
The most striking conclusion of their work is that the miniaturization limit is not a fixed and universal value. It directly depends on the "atomic recipe" used, i.e., the combination of materials.
By applying their platform to promising materials such as molybdenum disulfide (MoS₂), a 2D semiconductor, they observed that electron penetration varied greatly depending on the type of metal used for the electrode and the contact geometry.
Evolution of transistor design (source: TSMC)
This flexibility is excellent news. Simulations showed that by choosing the right combination of materials, it was possible to eliminate electron leakage for dimensions well below current standards.
One of the optimal configurations achieved a critical size below 4 nanometers, demonstrating that there is still significant room for progress beyond current 2nm lithography technologies.
What is the real impact for the semiconductor industry?
The impact of this advance is primarily economic and strategic. Rather than embarking on long and risky development cycles, chip designers now have a kind of "virtual roadmap".
They can explore hundreds of material combinations and designs on computers to identify the most promising ones, thus significantly reducing R&D costs and timelines.
Ultimately, this method paves the way for the design of next-generation chips, particularly for power-hungry applications like artificial intelligence and high-performance computing (HPC), with perfectly optimized material and geometry combinations.
As Professor Kim points out, this study "presents a new physical criterion" for defining transistor limits. By analyzing quantum phenomena difficult to probe experimentally, his team has created a bridge between fundamental research and the design of concrete products that will equip our future devices.
